Ver 1.3.36-2 Description:
Structural Verilog compiler for UNIX operating systems.
Structural Verilog compiler for UN*X operating systems. Some synthesizable behavioral constructs are now supported. An event simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco/csim) is included which can compile netlists into fast levelized C code. Cyco can also generate ABEL netlists that may be used for FPGA generation. GTKWave, a fully-featured wave viewer is quite functional now. (requires GTK+ -1.2.0 or greater).
To conclude Ver works on Linux operating system and can be easily downloaded using the below download link according to GNU Public License license.
Ver was filed under the Science category and was reviewed in softlookup.com and receive 2/5 Score.
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Popularity 4/10 - Downloads - 200 - Score - 2/5
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