Covered  (0.3) Free Download

Covered 0.3 Description:
Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, combinational logic and finite state machine (FSM) coverage analysis. Verilog source files are parsed along with VCD dumpfiles to create Coverage Description Database (CDD) files which can be merged with other CDD files generated from the same design and/or have reports generated from them through the use of the merge and report commands, respectively.

Covered: Verilog code coverage analysis utility.
Publisher: Trevor Williams
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Category: Science 
Publisher: Trevor Williams      More titles >>
Last Updated: 03/12/2019
Requirements: Not specified
License: GNU Public License
Operating system: Linux
Hits: 204
File size: Not specified
Price: Not specified

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